1. Field of the Disclosure
The disclosure relates generally to clock distribution network architectures and, more particularly, to clock distribution network architectures for resonant-clocked systems.
2. Brief Description of Related Technology
Resonant clocking has been recently proposed for the design of energy-efficient clock distribution networks in synchronous digital systems. In resonant clocking, energy efficient operation is achieved by using an inductor to resonate the parasitic capacitance of the clock network. For any given resonant clock network, increasing inductor size results in lower energy dissipation but, at the same time, slower operating speed. Conversely, decreasing inductor size increases operating speed but also results in increased energy dissipation. Energy dissipation also depends on overall clock network resistance, with larger resistance resulting in higher energy dissipation and vice versa. Therefore, the design of large resonant clock networks that operate with high energy efficiency at high clock speeds presents a significant technical challenge.
Energy efficiency and operating speed aside, standard digital and mixed-signal design flows typically require that resonant clock networks operate in synchrony with a reference clock signal. Furthermore, to attain high performance, such networks attempt to exhibit low skew in clock arrival times across the entire chip. Another desirable property of clock networks in general is that their timing characteristics be relatively immune to variations in the fabrication process, operating conditions, and environmental conditions. Therefore, the design of large, fast, and energy-efficient resonant clock networks that achieve low clock skews, possess robust timing characteristics, and are directly compatible with standard digital and mixed-signal design flows represents a technical challenge of very substantial proportions.
One disclosure of design methods for resonant clock networks can be found in U.S. Pat. No. 5,734,285 (“Electronic circuit utilizing resonance technique to drive clock inputs of function circuitry for saving power”). A single resonant domain is described along with methods for synthesizing harmonic clock waveforms that include the fundamental clock frequency and a small number of higher-order harmonics. It also describes clock generators that are driven at a reference frequency, forcing the entire resonant clock network to operate at that frequency. However, the methods do not address scaling resonant clocking to encompass large chip-wide clock networks while achieving high energy efficiency.
Resonant clock network designs for local clocking (i.e., for driving flip-flops) are described and empirically evaluated in the following articles: “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al., International Symposium on Low-Power Electronic Design, August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications,” by Cooke, M., et al., International Symposium on Low-Power Electronic Design, August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al., Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004. The designs set forth in these papers are directed to a single resonant domain, however, and do not describe the design of large-scale chip-wide resonant clock networks. In the article by Drake, the authors evaluate resonant clocking for driving the last stage of a buffered clock network. However, they do not provide any methods for designing a large-scale chip-wide resonant clock network. Moreover, the clock generator at the root of the resonant clock network they evaluate is self-resonating and is not driven at the reference frequency of the clock signal that is distributed by the buffered clock network. Finally, they provide no methods for physical layout or skew management in a large-scale resonant clock.
The design and evaluation of resonant clocking for high-frequency global clock networks was addressed in “Design of Resonant Global Clock Distributions,” by Chan, S., et al., International Conference on Computer Design, 2003. This article focuses on global clocking, however, and does not provide any methods for designing a large-scale resonant network that distributes clock signals with high energy efficiency all the way to the individual flip-flops in a chip. Moreover, the clock generator described in this article is not driven by a reference clock and therefore, it is not straightforward to integrate in a standard digital design flow.